EverySpec Standards
Home > Library > NASA > NASA-GSFC > GSFC-Code-Series > 500-PG-8700-2-8

500-PG-8700.2.7, PROCEDURES AND GUIDELINES: FIELD PROGRAMMABLE GATE ARRAY (FPGA) DEVELOPMENT METHODOLOGY, NASA/GSFC (13 NOV 2006)

500-PG-8700.2.7, PROCEDURES AND GUIDELINES: FIELD PROGRAMMABLE GATE ARRAY (FPGA) DEVELOPMENT METHODOLOGY, NASA/GSFC (13 NOV 2006)., As FPGA technology advances, there is a growing trend for incorporating into these devices an increasing amount of the circuitry traditionally implemented as discrete digital components with degrees of complexity ranging from small to Very Large Scale Integration (VLSI). In some cases, the equivalent of an extremely large number of Printed Circuit Boards (PCB) based on such technology can be condensed into a single FPGA device. There is a need for FPGA development guidelines that ensure that adequate and consistent rules are applied to all FPGA designs, equivalent to those followed for traditional PCB implementations. This document establishes a methodology for the development of FPGA designs and is intended for use by engineering leads responsible for designs that include the use of FPGA devices. It is not concerned with detailed design guidelines, but rather with the development process itself. A separate document referenced in P.4, 500-PG-8700.2.7, covers specific technical recommendations for the design and evaluation of FPGA designs and is intended primarily for use by FPGA designers. The two documents are intended to compliment each other.

500-PG-8700.2.7

    
 Status:
Active

 FSC Code:
 AVCS - AVIONICS

Version:
11-200684.35 KB 500-PG-8700-2-8
08-2005434.65 KB 500-PG-8700-2-7

Simple Search
MilSpec Search



About Us   |   Terms of Use   |   DMCA   |   Privacy   |   EverySpec LLC © 2009 - 2022   All rights reserved.